A number of patents show that a semiconductor die (or "chip") can be "flip-chip" mounted and connected to another die (or "substrate") via a pattern or array of conductive bumps disposed one a surface of a semiconductor die. For example U.S. Pat. Nos. 4,825,284 and 4,926,241, incorporated herein by reference, describe method for "flip-chip" mounting of a semiconductor to a substrate by means of conductive (solder) bumps. Typically, the conductive bumps are ball-like structures formed of solder and disposed in a pattern on a surface of a die. A mating pattern of bond pads and/or similar conductive bumps is disposed on a surface of the substrate. The die is positioned over the substrate so that the die bumps are aligned with the substrate bumps, and the conductive bumps on the die are "re-flowed" or otherwise fused to their counterparts on the surface of the substrate to form electrical and mechanical connections between the die and the substrate.
Similar techniques are known in the art for mounting a packaged semiconductor device to a printed circuit board or other substrate. U.S. Pat. Nos. 4,700,276, 5,006,673, and 5,077,633, incorporated herein by reference, are generally directed to such techniques. Packaged semiconductor devices employing conductive bumps are commonly referred to as "pad array chip carriers". Other references to pad array chip carriers and similar mounting techniques are found in "Pad Array Improves Density" (Electronic Packaging and Production, May 1992, p. 25.), "Overmolded Plastic Pad Array Carriers (OMPAC): A Low-Cost, High Interconnect Density IC Packaging Solution for Consumer and Industrial Electronics", (Freyman and Pennisi, IEEE Publication No. 0569-5503/91/0000-176, 1991), and "LED Array Modules by New Technology Microbump Bonding Method" (Hatada, Fujimoto, Ochi, Ishida, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 13, No. 3, September 1990, pp. 521-527).
A related mounting technique is disclosed in U.S. Pat. No. 4,717,066, incorporated herein by reference, wherein a gold alloy is used for the conductive bumps (balls) rather than solder.
Hereinafter, all conductive bump connection techniques, both for chips (semiconductor dies, e.g., "flip-chip" mounting) and for packaged semiconductor devices (e.g., pad array chip carriers) will be referred to collectively as "micro-bump bonding".
Generally, as used herein, a micro-bump bonded assembly includes one or more relatively small silicon chips (or packages) mounted in face-to-face relationship to a larger silicon chip, package, or substrate. Solder balls (micro-bumps) are formed on the opposing (facing) faces of the chips (or packages) and the substrate, at a number of positions corresponding to one another. In other words, the pattern and spacing of the solder balls on the chip (or package) match the pattern and spacing of solder balls on the substrate. The chip (or package) is brought into face-to-face relationship with the substrate, and when the solder balls of the chip (or package) are aligned with the solder balls of the substrate, the chip (package) and substrate are subjected to heat, which (ideally) causes the solder balls of the chip (package) to fuse with the corresponding solder balls of the substrate.
Generally, conductive bumps such as solder balls are formed on conductive pads (bond pads) disposed on a surface of a die or substrate. These bond pads are generally either rectangular or circular.
FIG. 1a shows a typical rectangular bond pad 110a. The corners of such rectangular bond pads are often rounded, as shown in the figure. Sometimes such rectangular bond pads are somewhat elongated, rather than substantially square, as shown.
FIG. 1b shows a typical "round" bond pad 110b. As shown in the figure, the bond pad 110b is substantially circular. Sometimes, "round" bond pads may be somewhat elliptical in shape, rather than substantially circular, as shown.
FIG. 1c shows a typical conductive bump contact 120 (e.g. solder bump)/disposed on a bond pad 110c. (The bond pad 110c is e.g., ford in a manner similar to the bond pad 110b of FIG. 1b.) As shown the conductive bump contact 120 has a convex-shaped surface. Often such conductive bumps 120 are formed by re-flowing a solder paste deposited on the bond pad 110c. Depending upon the amount of solder (paste) used, the shape of the conductive bump 120 after re-flowing may vary. Surface tension of the solder in the molten state dictates a convex shape. A relatively small amount of solder will form a conductive bump shaped similar to the conductive bump 120 in FIG. 1c. On a rectangular bond pad (e.g., 110a FIG. 1a) such a conductive bump would have a "pillow" shape, while on a round bond pad, it would have a more hemi-spherical (spherical sectional) shape. However, a relatively large amount (glob) of solder paste will, when re-flowed, form a large ball-like (more completely spherical) structure (not shown) atop the bond pad 110c.
Various problems may attend such micro-bump formation and bonding techniques, particularly regarding the formation of reliable solder joints between the solder balls of the chip and the solder balls of the substrate. For example, as disclosed in commonly-owned U.S. Pat. No. 5,111,279, incorporated by reference herein, applying liquid flux to the entire surface of the substrate, prior to placing a chip on a substrate, can cause the chip to be drawn (migrate) to the center of the substrate due to capillary action and/or surface tension. As further disclosed in the patent, it is sometimes difficult to ensure that the solder balls of the chip will successfully fuse to the solder balls of the substrate. Further, as disclosed in the patent, the mechanical structure resulting from the solder balls fusing together may be somewhat indeterminate. The patent discloses a preformed planar structure inserted between the chip and the substrate to help overcome these problems.
U.S. Pat. No. 4,545,610, incorporated by reference herein, discloses a technique for forming "elongated" micro-bump solder connections between a package and a substrate, thereby controlling, to some degree, the shape of the solder connection and the spacing between the package and the substrate.
Another problem attendant with micro-bump assembly of a chip to a substrate (both having solder bumps) is that in the process of placing a solder-bumped integrated circuit (chip) onto a substrate, it is common to have some problems placing the chip without the chip slipping out of alignment. If both sets of solder bumps have been reflowed, alignment of the chip involves "balancing" one solder bump ball on top of another solder bump ball. Evidently, a ball does not inherently want to rest upon another ball, this being an unstable configuration which is subject to misalignment of the chip with the substrate, such as in response to mechanical vibration and the like.
This "balancing act" problem is illustrated in FIG. 2. A semiconductor device 225 has a raised conductive bump contact 220b formed on a bond pad 210b on a surface of the semiconductor device 225. A substrate 205, to which the semiconductor device 225 is to be assembled to form a semiconductor device assembly 200, has a bond pad 210a with a similar, mating conductive bump 220a. The semiconductor device 225 is positioned over the substrate 205 such that the two conductive bump contacts 220a and 220b (typically formed of solder) come into contact with one another. In a subsequent step, the conductive bump contacts 220a and 220b will be fused (typically by heat-induced re-flow of the solder) to form a single electrical and mechanical connection between the semiconductor device 225 and the substrate 205. Evidently, the interface between the bump contacts 220a and 220b, as shown, is an unstable one if the semiconductor device 225 is not mechanically "registered" to the substrate 205. Without such mechanical registration, it is relatively easy for the conductive bump contact 220b on the semiconductor device 225 to slide off of the conductive bump contact 220a on the substrate 205.
It is known to provide for positive mechanical registration between a semiconductor device and a substrate by securely `chucking` the semiconductor device (e.g., chip), i.e., holding it in precise mechanical alignment with the substrate during the assembly process (i.e., while the solder balls are being fused to one another), to avoid movement (misalignment) of the semiconductor device (chip) due to surface tension and/or capillary action (i.e., caused by liquid flux) and/or mechanical vibration during the flip-chip assembly process.
Several other techniques are known for improving alignment during micro-bump bonding. U.S. Pat. No. 3,811,186, incorporated by reference herein, describes a technique whereby a self-aligning spacer is disposed between the die or package and the substrate. The spacer is sized to nearly exactly fit between the conductive bumps on the substrate (and between the conductive bumps on the package or die) thereby providing spacing and registration between the substrate and the die or package.
Another self-alignment technique for micro-bump bonding is describe in Japanese Patent No. 60-49638 (A), wherein conductive pads on a die-receiving substrate are "dented" in a pattern to match the conductive bumps on the die (i.e., holes are formed in substrate positioned to "capture" the bumps on the die). While this technique does improve alignment during assembly, it suffers from many of the other problems described hereinabove, e.g., uncertain contact shape and height of the ultimate solder joint, uncertain spacing between the die and the substrate, etc..